IEC-61523-1 › Delay and power calculation standards - Part 1: Integrated Circuit (IC) Open Library Architecture (OLA)
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IEC 61523-1:2023 focuses on delay and power calculation for integrated circuit design with support for modeling logical behavior and signal integrity.
The standard specifications covered in this document are as follows:
- Description language for timing and power modeling, called the .delay calculation language. (DCL)
- Software procedural interface (PI) for communications between EDA applications and compiled libraries of DCL descriptions
- Standard file exchange format for parasitic information about the chip design: Standard Parasitic Exchange Format (SPEF)
- Informative usage examples
- Informative notes.
This is an IEC/IEEE dual logo standard.
To find similar documents by classification:
25.040 (Industrial automation systems IT applications in industry, see 35.240.50)
25.040.01 (Industrial automation systems in general)
35.060 (Languages used in information technology)
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Document Number
IEC 61523-1 Ed. 3.0 en:2023
Revision Level
EDITION 3.0
Status
Current
Publication Date
Oct. 1, 2023
Committee Number
91