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This standard was transferred to SEMI (www.semi.org) May 2003

1.1 This practice is used to detect shallow etch pits, which may be related to the level of metallic impurities near the surface of silicon epitaxial or polished wafers.

1.2 This practice is not recommended for use in defect density evaluations, but as a subjective means of estimating defect densities and distributions on the surface of a polished or epitaxial wafer.

1.3 Silicon crystals doped either p- or n-type and with resistivities as low as 0.005 Ω ·cm may be evaluated. This practice is applicable for silicon wafers grown in either a (111) or (100) crystal orientation.

1.4 This practice utilizes a thermal oxidation process followed by a chemical preferential etchant to create and then delineate shallow etch pits.

1.5 The values stated in acceptable metric units are to be regarded as the standard. The values in parentheses are for information only.

1.6 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use. Specific hazard statements are given in Section 9.

Keywords

epitaxial; oxidation; preferential etch; saucer pit; shallow etch pit; silicon; ICS Number Code 29.045 (Semiconducting materials)

To find similar documents by ASTM Volume:

10.04 (Electronics; Declarable Substances in Materials; 3D Imaging Systems)

To find similar documents by classification:

29.045 (Semiconducting materials)

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