ASTM-F615M Standard Practice for Determining Safe Current Pulse-Operating Regions for Metallization on Semiconductor Components (Metric) (Withdrawn 2022)

ASTM-F615M - 1995 R13 EDITION - CANCELLED
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Standard Practice for Determining Safe Current Pulse-Operating Regions for Metallization on Semiconductor Components (Metric) (Withdrawn 2022)

Scope

1.1 This practice covers procedures for determining operating regions that are safe from metallization burnout induced by current pulses of less than 1-s duration.

Note 1In this practice, “metallization” refers to metallic layers on semiconductor components such as interconnect patterns on integrated circuits. The principles of the practice may, however, be extended to nearly any current-carrying path. The term “burnout” refers to either fusing or vaporization.

1.2 This practice is based on the application of unipolar rectangular current test pulses. An extrapolation technique is specified for mapping safe operating regions in the pulse-amplitude versus pulse-duration plane. A procedure is provided in Appendix X2 to relate safe operating regions established from rectangular pulse data to safe operating regions for arbitrary pulse shapes.

1.3 This practice is not intended to apply to metallization damage mechanisms other than fusing or vaporization induced by current pulses and, in particular, is not intended to apply to long-term mechanisms, such as metal migration.

1.4 This practice is not intended to determine the nature of any defect causing failure.

1.5 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.

Significance and Use

4.1 Solid-state electronic devices subjected to stresses from excessive current pulses sometimes fail because a portion of the metallization fuses or vaporizes (suffers burnout). Burnout susceptibility can vary significantly from component to component on a given wafer, regardless of design. This practice provides a procedure for establishing the limits of pulse current overstress within which the metallization of a given device should survive.

4.2 This practice can be used as a destructive test in a lot-sampling program to determine the boundaries of the safe operating region having desired survival probabilities and statistical confidence levels when appropriate sample quantities and statistical analyses are used.

Note 2The practice may be extended to infer the survivability of untested metallization adjacent to the specimen metallization on a semiconductor die or wafer if care is taken that appropriate similarities exist in the design and fabrication variables.

Keywords

current pulse; current pulse burnout; metallization burnout; safe current pulse; semiconductor burnout

To find similar documents by ASTM Volume:

10.04 (Electronics; Declarable Substances in Materials; 3D Imaging Systems)

To find similar documents by classification:

29.045 (Semiconducting materials)

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Document Number

ASTM-F615M-95(2013)

Revision Level

1995 R13 EDITION

Status

Cancelled

Modification Type

Withdrawn

Publication Date

May 15, 2013

Document Type

Practice

Page Count

5 pages

Committee Number

F01.11