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Standard Test Method for Characterizing Semiconductor Deep Levels by Transient Capacitance Techniques

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Standard Test Method for Characterizing Semiconductor Deep Levels by Transient Capacitance Techniques (Withdrawn 2003)


1.1 This test method covers three procedures for determining the density, activation energy, and prefactor of the exponential expression for the emission rate of deep-level defect centers in semiconductor depletion regions by transient-capacitance techniques. Procedure A is the conventional, constant voltage, deep-level transient spectroscopy (DLTS) technique in which the temperature is slowly scanned and an exponential capacitance transient is assumed. Procedure B is the conventional DLTS (Procedure A) with corrections for nonexponential transients due to heavy trap doping and incomplete charging of the depletion region. Procedure C is a more precise referee technique that uses a series of isothermal transient measurements and corrects for the same sources of error as Procedure B.

1.2 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.


activation energy; deep levels; DLTS; semiconductor silicon; trap density; transient capacitance; ICS Number Code 29.045 (Semiconducting materials)

To find similar documents by ASTM Volume:

10.04 (Electronics; Declarable Substances in Materials; 3D Imaging Systems)

To find similar documents by classification:

29.045 (Semiconducting materials)

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Document Number


Revision Level

1990 R96(E1) EDITION



Modification Type

Reapproval with Ed Change

Publication Date

Jan. 1, 1996

Document Type

Test Method

Page Count

8 pages

Committee Number